A/D converters using absolute-value algorithms achieve high conversion speed because clocking is generally not necessary. Referring to FIG. 1, it illustrates a conventional absolute-value converter in which an analog voltage signal V.sub.I is converted into an N-bit digital signal represented as bits 1, 2, . . . J, . . . N-1 and N. Bit 1 is the most significant bit (MSB), while bit N is the least significant bit (LSB).
In this converter, an input circuit 10 operates on analog voltage V.sub.I to produce an analog input signal V.sub.I1 which is supplied to the first amplifier A.sub.1 in a chain of N-1 main absolute-value differential amplifiers A.sub.1, A.sub.2, . . . A.sub.J, . . . and A.sub.N-1. Upon receiving a mainline input signal V.sub.IJ and a reference input signal, each amplifier A.sub.J amplifies the absolute value of their voltage difference to produce an output signal V.sub.OJ which is supplied as the mainline input V.sub.IJ+1 to the next amplifier A.sub.J+1. This procedure is followed with all of outputs V.sub.OJ except output V.sub.ON-1 which is supplied as mainline input V.sub.IN to a buffer 12 that receives a reference input but may not be an absolute-value differential amplifier.
A set of N comparators C.sub.1, . . . C.sub.J, . . . C.sub.N-1, and C.sub.N corresponding respectively to amplifiers A.sub.1, . . . A.sub.J, . . . and A.sub.N-1 and buffer 12 generates the digital signal. In particular, each comparator C.sub.J generates bit J using the inputs to corresponding amplifier A.sub.J or buffer 12. Typically, comparator C.sub.J does not directly compare these inputs but instead compares a pair of intermediate signals V.sub.YJ and V.sub.ZJ generated from the inputs. The generation of signals V.sub.YJ and V.sub.ZJ is represented by the dashed lines within each amplifier A.sub.J or buffer 12.
In a common absolute-value converter, each amplifier A.sub.J has an optimum gain of precisely 2. Mainline inputs V.sub.I1 -V.sub.IN all vary over the same voltage range from a lower end-point level V.sub.L to an upper end-point level V.sub.U, both of which are normally fixed. The reference inputs to amplifiers A.sub.1 -A.sub.N-1 and buffer 12 are all at the mid-range level (V.sub.U +V.sub.L)/2. Neglecting any gain error or offset in output V.sub.OJ from its nominal value, output V.sub.OJ is given by the transfer function 2.vertline.V.sub.IJ -(V.sub.U +V.sub.L)/2.vertline.+V.sub.L for each amplifier A.sub.J. Setting V.sub.IJ as either V.sub.L or V.sub.U yields V.sub.U as the maximum V.sub.OJ output, while entering (V.sub.U +V.sub.L)/2 into this transfer function yields V.sub.L as the minimum V.sub.OJ output. These extreme V.sub.OJ values are precisely the necessary voltage range for the next input V.sub.IJ+1.
Offsets and gain errors resulting, for example, from temperature variation and manufacturing imprecision can cause errors in the digital signal. Some prior absolute-value A/D converters have used complicated precision amplifier cells to overcome this problem. These cells occupy a relatively large area which makes this solution undesirable. In addition, conversion speed is limited because large amounts of feedback are needed.
Another solution suggested by G. J. J. Vos in "een snelle 8-bits analoog/digitaalomzetter", Polytechnisch Tijdschrift, Elektrotechnick/Elektronica, Vol. 35, Feb. 1980, pp. 112-118, is to regulate amplifiers A.sub.1 -A.sub.N-1 with an open-loop control system represented as item 14 in FIG. 1. As the Vos control system is understood, it basically attempts to force the offset of each amplifier A.sub.J to zero. Incidental to this offset control, the Vos system also appears to provide some gain regulation. Although Vos is a step forward, its open-loop control is still relatively imprecise.
FIG. 2 shows the basic bipolar circuit that Vos uses for each amplifier A.sub.J. Inputs V.sub.IJ and (V.sub.U +V.sub.L)/2 are supplied respectively to the bases of a pair of NPN transistors Q1.sub.A and Q1.sub.B whose emitters are coupled to each other through a pair of resistors R1.sub.A and R1.sub.B separated by a node 16. Transistors Q1.sub.A and Q1.sub.B amplify the voltage difference between their bases. Their collectors supply the amplified difference to the bases of a pair of NPN transistors Q2.sub.A and Q2.sub.B, respectively, whose emitters which are tied together at a node 18 provide the absolute value of the amplified difference to one end of resistor R.sub.A. Output V.sub.OJ is taken at the other end of resistor R.sub.A. The collectors of transistors Q2.sub.A and Q2.sub.B are cross-coupled to their bases through a pair of resistors R2.sub.B and R2.sub.A, respectively, and to a source of a high supply voltage V.sub.CC through a pair of resistors R3.sub.B and R3.sub.A, respectively. The purpose of the cross-coupling is to cause output V.sub.OJ to vary linearly with mainline input V.sub.IJ when it is near the reference input.
A current source consisting of an NPN transistor Q3 and a resistor R.sub.G connected together between node 16 and a source of a low supply voltage V.sub.EE provides the operating current for transistors Q1.sub.A and Q1.sub.B. Likewise, a current source consisting of an NPN transistor Q4 and a resistor R.sub.B connected together between the V.sub.EE supply and resistor R.sub.A provides the operating current for transistors Q2.sub.A and Q2.sub.B. Control system 14 drives the bases of transistors Q3 and Q4 in an effort to reduce the offset to as low a value as possible, preferably zero. As pointed out above, system 14 also incidentally appears to affect amplifier gain. This general type of absolute-value differential amplifier is particularly suitable for absolute-value D/A converters because of its overall simplicity and its capability for good input-to-output linearity.